//////////////////////////////////////////////////////////////////////////////////
// INSTITUTION:    Xidian University
// DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
// 
// Create Date:    16:53:58 02/14/2016 
// Design Name:    PWM_COUNTER 
// Module Name:    PWM_COUNTER 
// Project Name:   PWM
// Target Devices: EP3C16F484C6
// Tool versions:  Quartus II 13.1
// Design Lauguage:Verilog-HDL
// Dependencies:   -
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: Modulus = 10(0-9)
//                      
//
//////////////////////////////////////////////////////////////////////////////////
module PWM_COUNTER (
									input 				i_pwm_clk,
									input					i_sys_rst,
									output reg[6:0]	o_pwm_val
								);
								
parameter  cnt_mod_value = 7'd100;
parameter  cnt_mod_compare_value = cnt_mod_value - 7'd1;
				
always @ (posedge i_sys_rst or posedge i_pwm_clk)
begin
	if( i_sys_rst )begin
		o_pwm_val <= 7'd0;
	end else begin
		if( o_pwm_val == cnt_mod_compare_value )begin
			o_pwm_val <= 7'd0;
		end else begin
			o_pwm_val <= o_pwm_val + 7'd1;
		end			
	end
end

endmodule
